Introduction
Even though the high-frequency processors from AMD, Alpha, Intel and IBM pretty much stole the show at the recent International Solid-State Circuits Conference (ISSCC) in San Francisco, there were several new processor designs that deserve attention as well. They are based on new architectural concepts and continue the design trends of increased integration, higher parallelism, and innovation in low-power optimization. Many of these advances are made possible by the latest 0.18µ process technology that enables twice the number of devices per unit area, operating faster and consuming less power per operation compared to the previous generation.
C-Port Corp. and NEC for example introduced papers on processors with new levels of chip integration, including 17 and 4 independent processing units respectively. Each of these on-chip processsor units operates on its own instruction stream and greatly expands the performance and flexibility of the chip. These kinds of integration levels are achieved by increasing the number of transistors.
Glenn Giacalone, Consulting Engineer at C-Port presented a paper on a digital communications processor (DCP) that uses a whopping 56 Million transistors and is a multiple-instruction, multiple-data (MIMD) general-purpose communications processor implemented in a 0.25µ dual-gate n-well CMOS process with 6 layers of Aluminum metal. The DCP contains 16 channel processors, a fabric port processor, a table look-up unit, a queue-management unit, a buffer management unit and an executive processor on a single chip operating at 200 MHz. This architecture allows the handling of different communication protocols with various custom features that may be added through software modification. These modifications may be made either in micro-code running on the serial data processors or in high-level applications and libraries running on RISC cores. Among the supported applications are packet-over-Sonet, ATM switching, AAL5 SARs and Gigabit Ethernet.
NEC’s chip, presented by Research Manager Naoki Nishi integrates four tightly-coupled processors. It consumes only 1 W at 125 MHz clock frequency and 1 GIPS drawing 1,3 V. It is aimed at low-power embedded systems, especially smart information terminals. The chip also contains a power-management unit (PMU) that cuts off the leakage current of each power-control domain independently using dedicated power switches. For stand-by mode the PMU has on-chip power switches, which control cache subsystem and MPU (Multi Processing Unit) core logic separately. The MPU consumes only 0.22 mW when all switches are turned off and 9.56 mW with the cache subsystem switch on. Naoki also showed results for an IDCT program in MPEG-2 decoding: the MPU uses 0.92 W.
The more, the better …
Additional transistors in new design are also applied to the ever-increasing instruction level parallelism achieved by traditional single-instruction stream processors. Sun Microsystems for example presented a new SPARC processor that executes up to 7 instructions per clock compared to 4 instructions in the previous generation. The chip also utilizes more than twice as many transistors than its earlier counterparts to achieve the increased performance.
Sun’s Dale Greenly introduced the UltraSPARC-III, a 4-instruction-issue superscalar 64-bit microprocessor running at 800 MHz that is targeted at high-performance desktop workstations, work group servers, and enterprise server platforms. On-chip caches include a 64 KByte 4-way associative data cache, 32 KByte 4-way associative instruction cache, a 2 KByte 4-way associative data prefetch cache, and a 2 KByte 4-way associative write cache. The chip contains 23 Million transistors and consumes 60 W at a power supply of 1.5 V. According to Sun the architecture is driven by performance, scalability and compatibility. Being SPARC V-9 compliant, the design maintains binary compatibility with all existing SPARC applications.
