Introduction
The second day (Microprocessor Forum 1997 — First Day) of the Microprocessor Forum is filled with announcements of all the CPU manufacturers, AMD will tell us about the future of the K6, C6 will let us know what happens to the WinChip C6 in the next months and Intel will supply us with information about the Deschutes and the upcoming IA64 architecture of the Merced processor.
Announcements
This year still the K6 is supposed to ship in the shrunk 0.25 micron version, which will reduce the die size from 162 mm² down to 68 mm2. This will offer higher clock speeds and the chip will require less power. 300 MHz and more will be possible, whilst the K6 will run at only 2.5 V.
The AMD K6 3D CPU
The next step will be the ‘K6 3D‘ in the first half of 1998. The K6 3D’s features will be the following:
- AMD 3D Technology
- Instruction set extensions to accelerate 3D graphics, audio and other multimedia applications
- Superscalar MMX Unit
- Dual decode and dual execution pipelines
- Maintains the K6 advantage of low execution latencies
- No decode pairing restrictions
- Only one cycle misalignment penalty on memory accesses
- Increases local bus and L2 cache bandwidth by 50%
- Redesigned I/O timing to allow for low cost 100 MHz motherboard
The 3D instructions will accelerate floating point computations and multiple floating point instructions can be executed per clock. The instructions were defined and implemented in collaboration with leading ISV’s. Here’s some more detail:
- SIMD (single instruction multiple data) floating point instructions
- supports IEEE single precision data type
- two 32-bit FP values per 64-bit reg/mem operand
- using MMX registers
- saturating arithmetic
- no exceptions
- limited rounding modes
- no switching overhead between MMX and AMD-3D instructions
- avoid x87 register stack
These new instructions will unfortunately be proprietary to AMD, although Jerry Sanders was offering to license it. Michael Slater is right to say that now it’s too late, since other vendors are already going into their own directions. AMD will (have to) supply a dedicated AMD development support group for their new instructions.
The superscalar MMX unit will certainly speed up the K6’s MMX performance significantly, but I was waiting for an improved and superscalar FPU as well. The 100 MHz bus speed story is nothing too new for readers of this website and we are all looking forward to it. The K6 3D is supposed to ship as a 300 MHz version initially, closely followed by a 350 MHz part. AMD plans to present K6 3D CPUs at Comdex for the first time. Let’s hope I’ll get one earlier.
The AMD K6+ 3D CPU
Now there’s the ‘+’ eventually, already published in the wrong context all over the web. The K6+ 3D will be a screamer, but we’ll have to wait until the second half of 1998 until it will ship. The coolest feature of this CPU will be the on-chip L2 cache of 256 kB. This is not the same as what you can currently find in Intel Pentium Pro CPUs, since there it’s an additional L2 cache chip. This on-chip L2 cache will make the motherboard cache to a L3 cache as known from Digital’s Alpha CPU. The AMD K6+ 3D CPU is supposed to start off with 350 MHz, then quickly moving to 400 MHz and more.
Here are some more details:
- On Chip Full Speed Backside Level 2 Cache
- operates at 1x processor frequency
- 4-1-1-1(-1-1-1-1) access timing (peak bandwidth 3.2 GB/s at 400 MHz)
- 256 kB
- 4 way set associative
- 100 MHz front side bus
- optional very large frontside level 3 cache
The K7 CPU
Jerry Sanders gave us the chance of a sneak preview at the K7. The picture looked like my old picture of the open Klamath cartridge, only with ‘AMD K7’ printed on the green BGA chip. This CPU will fit into Slot 1!!! AMD calls it ‘Slot A’ though and it will use the ‘Alpha’ EV6 bus protocol. I wonder what’s that all about, since it doesn’t sound as if the K7 will run in Pentium II boards. I’ll try getting some clarification here. It’s supposed to start shipping sometime 1999 at 500 MHz initially.
Super 7
This is what AMD calls the Socket 7 motherboards with AGP and 100 MHz bus speed. It is supposed to happen in the first half of next year and you will certainly agree with me that this is about time. AMD will probably reach this with the help of independent chipset makers. I hope AMD will be able to see the importance of close and fruitful cooperation with these chipset manufacturers, since both of them need each other to survive. AMD would be in a much better position if they could supply their own chipset without depending on other chipset manufacturers, but so far a chipset that’s designed and manufactured by AMD remains to be seen.
Intel Announcements
IA32
Intel was announcing pretty much the same as what I published several months ago on the Intel Roadmap Page. The Deschutes will be a quarter micron version of the Pentium II. It will come in two flavors, for Slot 1 and Slot 2. The Slot 1 Deschutes, which will still be called ‘Pentium II’, will commence with 333 MHz at 66 MHz bus and later move to 100 MHz bus with 350, 400 MHz and beyond. This Slot 1 CPU will most likely stay limited to 512 MB of RAM support as with the current Pentium II and it will certainly not support more than dual CPU systems. The Slot 2 Deschutes, which hasn’t got a name yet, will be targeted to high end server systems, replacing the old and gray Pentium Pro. It will come with a faster and larger cache, running at clock speed, it will commence with 100 MHz bus speed and you will be able to use it in quad CPU configuration as well. The 512 MB RAM limitation should be solved for Slot 2 as well, although Intel never mentioned it today. The Slot 2 Deschutes will commence at 350 MHz, then moving to 400 and 450 MHz until end 1998. Both Deschutes will probably be launched in the second half of 1998, the Slot 1 version maybe a little earlier.
IA64
The architectural overview of the new architecture for the Merced processor takes a while to explain. I will publish this in a few days.
Cyrix Announcements
Surprise surprise, there’ll be a 100 MHz bus speed support of the 6x86MX CPU as well pretty soon, but that together with faster clock speeds will be all that happens with 6x86MX CPUs until mid 1998.
The next version of the 6x86MX CPU has got the codename ‘Cayenne‘. It is supposed to ship in the second half of 1998 and besides some house keeping issues as virtual mode enhancements and frequency optimizations it will have the following enhancements:
- pipelined, dual issue FPU
- enhanced MMX technology
- .25 micron process technology
The FPU enhancements are certainly one of the most important things for the future of Cyrix CPUs and it remains to be seen how powerful this FPU will be. However, the data Cyrix showed looks like a doubling or maybe even tripling of the current 6x86MX FPU performance.
Behind the ‘enhanced MMX technology‘ stands something like what AMD calls ‘3D enhancements’. It is the proprietary instruction set extension of Cyrix, called ‘MMXFP‘. It’s also supposed to SIMD single precision FPU executions and shall reach more than 1 GFLOP of peak performance.
The ‘Cayenne’ is supposed to run at PR300 to PR400 and will have a 65 mm² die size in .25 micron/5 metal layer technology.
IDT Announcements
IDT announced more or less what I already mentioned on my C6 review page. There’ll be 225 and 240 MHz C6 CPUs out in November. The C6+ is supposed to ship in spring next year and it will have a faster FPU, that is supposed to be as fast as the FPU of the Pentium MMX, as well as an improved MMX unit, supposedly faster than the Pentium MMX. You will certainly not be surprised about the fact that the C6+ will also have its proprietary set of new ‘3D instructions’, also capable of SIMD FPU executions.
The C6+ will also have integer enhancements, so that the chip will overall be a lot faster than the current C6. The die size will also shrink down to .25 micron and the clock speeds will go up as well as the power consumption will go down. The C6+ will also run at 100 MHz bus speed by mid of next year.
Eventually IDT will also include a 256 kB L2 cache into the chip as AMD will do with their K6+ 3D.
The expected clock speeds of the C6+ will be up to 300 MHz sometimes in the second half of 1998
